Building a RISC-V CPU Core

Building a RISC-V CPU Core is designed for anyone with a technical inclination who is interested in learning more about hardware. Whether you are new to digital logic or are a seasoned veteran, students will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required. LFD111x is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE. This course is a hands-on experience with RISC-V and modern circuit design tools. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog). 3b

• Digital logic design (combinational and sequential logic)
• RISC-V (RV32I) instruction set architecture
• Basic CPU microarchitecture
• Transaction-Level Verilog basics
• Makerchip online IDE

• The lab environment (Makerchip) is entirely online. The only system requirement is a web browser.You may want to consider first taking Introduction to RISC-V (LFD110x) on edX, though this is not a prerequisite.