VLSI Chip Design and Simulation with Electric VLSI EDA Tool

This course provides a comprehensive exploration of CMOS VLSI design and simulation, covering IC technology, CMOS structures, historical timelines, processor intricacies, MOS transistor design, non-ideal characteristics, power dissipation, low-power design techniques, and practical insights into CMOS logic gates. Participants will delve into fundamental components and circuit design in the "Analog Circuit CMOS Chip Design and Simulation" module, using the Electric VLSI EDA tool. This includes stick diagrams, tool installation and usage, and hands-on experience in schematic/layout representations, enhancing electronic circuit design proficiency. In the "Digital Circuit CMOS Chip Design and Simulation" module, participants create systematic workflows for schematic/layout designs using the Electric VLSI EDA tool. The curriculum covers logic gates, and half adder circuits, providing a holistic understanding of CMOS logic circuit design. Throughout the course, participants acquire a robust skill set, combining theoretical knowledge with practical expertise in CMOS VLSI design and simulation. By the end of this course, you will be able to:  Develop a profound understanding of Integrated Circuit (IC) technology, exploring its historical timeline and key inventions.  Discuss Moore’s Law and technology scaling, recognizing the importance of processors in Very Large-Scale Integration (VLSI).  Gain proficiency in MOS transistors, explaining their types and comprehending their working process, including operational modes of both PMOS and NMOS transistors.  Describe ideal transistor I-V characteristics and delve into non-ideal transistor characteristics, including leakage currents and their impact on device performance.  Understand the workings of the CMOS inverter, covering both its static behavior and power dissipation characteristics.  Explain components and mechanisms involved in CMOS power dissipation, addressing both static and dynamic aspects.  Explore benefits of low-power design techniques, analyzing factors influencing power consumption, and learning various power reduction techniques.  Understand the purpose of power gating in reducing overall power consumption and learn techniques to minimize short-circuit power consumption.  Explain the fundamentals of CMOS logic gates, including the series and parallel connections of NMOS and PMOS transistors.  Acquire skills in designing basic logic gates using Complementary Metal-Oxide-Semiconductor (CMOS) technology.  Develop skills in designing CMOS circuits using stick diagrams, creating blueprints for physical layouts adhering to semiconductor manufacturing process design rules.  Install and set up Electric VLSI EDA tool for VLSI circuit design, exploring components, schematic and layout editors, and conducting essential checks.  Understand PMOS and NMOS transistor concepts, design schematic and layout representations, perform various checks, and conduct simulations for current-voltage characteristics.  Grasp the CMOS inverter concept, create schematic and layout designs, and simulate the inverter to analyze behavior and characteristics.  Explore common-source and common-drain amplifiers in analog circuit design, designing schematics, layouts, and performing simulations to analyze performance.  Investigate the three-stage oscillator concept, design schematics and layout representations with CMOS inverters, and analyze performance through waveform simulations.  Comprehend CMOS NAND gate concepts, design schematics, validate layouts, and simulate for logical behavior analysis with diverse input scenarios.  Explore various digital circuit elements such as AND, NOR, and OR gates, XOR gate, and half adder, designing schematics, layouts, and performing simulations

• Develop a deep understanding of IC technology and history
• Explain MOS transistor types and functions
• Evaluate non-ideal transistor characteristics and impacts
• Describe CMOS inverter operation and power characteristics
• Apply low-power design techniques including power gating
• Design CMOS logic gates and layouts using stick diagrams

• Professional experience in CMOS VLSI design or semiconductor manufacturing